參數(shù)資料
型號(hào)： XC5202-6PQ160C
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 26/73頁(yè)
文件大?。?/td> 598K
代理商： XC5202-6PQ160C
R
XC5200 Series Field Programmable Gate Arrays
7-108
November 5, 1998 (Version 5.2)
Configuration Sequence
There are four major steps in the XC5200-Series power-up
configuration sequence.
Power-On Time-Out
Initialization
Configuration
Start-Up
The full process is illustrated in
Figure 24
.
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When V
CC
reaches the voltage at which portions
of the FPGA begin to operate (i.e., performs a
write-and-read test of a sample pair of configuration mem-
ory bits), the programmable I/O buffers are 3-stated with
active high-impedance pull-up resistors. A time-out delay
— nominally 4 ms — is initiated to allow the power-supply
voltage to stabilize. For correct operation the power supply
must reach V
CC
(min) by the end of the time-out, and must
not dip below it thereafter.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have com-
pleted initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper oper-
ation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM
pin Low. During all three phases — Power-on, Initialization,
and Configuration — DONE is held Low; HDC, LDC, and
INIT are active; DOUT is driven; and all I/O buffers are dis-
abled.
Initialization
This phase clears the configuration memory and estab-
lishes the configuration mode.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An
open-drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level on
INIT. The mode lines are sampled two internal clock cycles
later (nominally 2
μ
s).
The master device waits an additional 32
μ
s to 256
μ
s
(nominally 64-128
μ
s) to provide adequate time for all of the
slave devices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.
0
X2
2
3
4
5
6
7
8
9 10 11 12 13 14
1
X15
X16
15
SERIAL DATA IN
1
0 15 14 13 12 11 10 9
8
7
6
5
1
1
1
1
CRC – CHECKSUM
LAST DATA FRAME
S
X1789
Polynomial: X16 + X15 + X2 + 1
Readback Data Stream
Figure 23: Circuit for Generating CRC-16
Figure 24: Configuration Sequence
INIT
High if
Master
Yes
Sample
Mode Lines
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
3V
No
Yes
No
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3
μ
s per Frame
Master CCLK
Goes Active after
50 to 250
μ
s
F
Pull INIT Low
and Stop
X9017
EXTEST*
SAMPLE/PRELOAD*
BYPASS
CONFIGURE*
(*only when PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
uration
mFull
CoLength
Count
Completely Clear
Configuration
Memory
L
Boundary Scan
IAvailable:
I
Generate
One Time-Out Pulse
of 4 ms
PROGRAM
= Low
No
Yes
Yes
相關(guān)PDF資料
PDF描述
XC68341CFT16 Integrated Processor Users Manual
XC68341CFT25 Integrated Processor Users Manual
XC68341FT16 Integrated Processor Users Manual
XC68341FT16V Integrated Processor Users Manual
XC68341FT25 Integrated Processor Users Manual
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC5202-6PQ208C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5202-6PQ240C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5202-6TQ144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5202-6TQ176C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays
XC5202-6VQ10 制造商:Xilinx 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*