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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 434K |
| 代理商： | XC5000 |
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XC5200 Logic Cell Array Family
Preliminary
30
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Combinatorial Delays
F inputs to X output
DI inputs to DO output (Logic-Cell Feedthrough)
F inputs via F5_MUX to DO output
T
ILO
T
IDO
T
IMO
5.5
4.2
7.1
4.5
3.3
5.7
Carry Delays
Incremental delay per bit
Carry-in overhead from DI
Carry-in overhead from F
Carry-out overhead to DO
T
CY
T
CYDI
T
CYL
T
CYO
0.7
1.7
3.6
3.9
0.6
1.5
3.2
3.1
Sequential Delays
Clock (CK) to out (Q) (Flip-Flop)
Gate (Latch enable) going active to out (Q)
T
CKO
T
GO
5.4
8.6
4.4
6.8
Set-up Time Before Clock (CK)
F inputs
F inputs via F5_MUX
DI input
CE input
T
ICK
T
MICK
T
DICK
T
EICK
2.1
3.6
0.5
1.2
1.5
2.7
0.3
0.9
Hold Times After Clock (CK)
F inputs
F inputs via F5_MUX
DI input
CE input
T
CKI
T
CKMI
T
CKDI
T
CKEI
0
0
0
0
0
0
0
0
Clock Widths
Clock High Time
Clock Low Time
T
CH
T
CL
6.0
6.0
6.0
6.0
Reset Delays
Width (High)
Delay from CLR to Q (Flip-Flop)
Delay from CLR to Q (Latch)
T
CLRW
T
CLR
T
CLRL
6.0
6.0
7.3
6.1
5.8
4.8
Global Reset Delays (see Note 2)
Width (High)
Delay from internal GCLR to Q
T
GCLRW
T
GCLR
6.0
6.0
12.4
10.2
Note:
1.
The CLB K to Q output delay (T
CKO
) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (T
CKDI
) of any CLB on the same die.
Timing is based upon the XC5210 device. For other devices, see XACT Timing Calculator.
2.
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