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參數(shù)資料
| 型號(hào)： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大小： | 434K |
| 代理商： | XC5000 |
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IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Max
(ns)
Max
(ns)
Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
T
PI
T
PID
5.4
4.9
Pad to I (with delay)
11.1
10.2
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast)
T
OPF
T
OPS
T
TSONF
T
TSONS
T
GTSF
T
GTSS
4.6
4.5
Output (O) to Pad (slew-limited)
9.4
8.3
3-state to Pad active (fast)
6.9
6.6
3-state to Pad active (slew-limited)
11.6
10.4
Internal GTS to Pad active (fast)
17.7
15.9
Internal GTS to Pad active (slew-limited)
22.3
19.7
Note:
1.
Timing is measured at pin threshold, with 50-pF external capacitance loads.
Slew-limited
output rise/fall times are
approximately two times longer than
fast
output rise/fall times. For the effect of capacitive loads on ground bounce,
see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.
Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
2.
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