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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 31/48頁 |
| 文件大小： | 434K |
| 代理商： | XC5000 |
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27
Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
(ns)
Max
(ns)
Max
(ns)
TBUF driving a Longline
I to Longline, while TS is Low; i.e., buffer is constantly active
T
IO
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
4.0
4.0
3.6
3.6
TS going Low to Longline going from floating High or Low to
active Low or High
T
ON
5.3
5.3
4.8
4.8
TS going High to TBUF going inactive, not driving Longline
T
OFF
2.4
2.4
2.2
2.2
Note:
1.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
TS
I
O
TBUF
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