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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 30/48頁 |
| 文件大?。?/td> | 434K |
| 代理商： | XC5000 |
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XC5200 Logic Cell Array Family
Preliminary
26
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
(ns)
Max
(ns)
Max
(ns)
Global Signal Distribution
From pad through global buffer, to any clock (CK)
T
BUFG
XC5202
XC5204
XC5206
XC5210
XC5215
9.4
9.4
8.8
8.8
Internal Clock to Output Pad Delay
From clock (CK) to output pad (fast), using direct connect
between Q and output (O)
T
OKPOF
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
9.9
9.9
8.9
8.9
From clock (CK) to output pad (slew-limited), using direct
connect between Q and output (O)
T
OKPOS
14.8
14.8
12.7
12.7
Note:
1.
Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
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