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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大小： | 434K |
| 代理商： | XC5000 |
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R
19
Figure 16. Express Mode Programming Switching Characteristics
X6154
BYTE
0
CCLK
LCA Filled
1
2
3
INIT
T
DC
T
CD
T
IC
D0-D7
Serial Data Out
(DOUT)
RDY/BUSY
CS1
BYTE
1
BYTE
2
BYTE
3
Internal INIT
Description
Symbol
Min
Max
Units
CCLK
INIT (High) Setup time required
1
T
IC
5
μ
s
DIN Setup time required
2
T
DC
50
ns
DIN Hold time required
3
T
CD
0
ns
CCLK High time
T
CCH
50
ns
CCLK Low time
T
CCL
50
ns
CCLK Frequency
F
CC
10
MHz
Preliminary
Format
Table 6 describes the XC5200 configuration data stream.
Table 7 provides details of the internal configuration data
structure.
Configuration Sequence
Figure 17 illustrates the XC5200 start-up sequence. It is
described in detail in the sections below.
Clear Internal Logic
When reprogramming the XC5200 chip, a contention-free
state must be reached before memory initialization can
begin. In this state internal control lines sequence
activities in the following order: long lines are disabled,
output drivers are forced Low, and interconnect lines are
discharged. Each of these operations requires one cycle
of the 1-MHz Initialization clock. This sequencing is
important only when reprogramming, because the
contention-free state is immediately entered when
configuring from a power-on state.
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