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參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-179
XC4000XLA/XV FIeld Programmable Gate Arrays
6
Global Early Clock Input to Output Delay for BUFGE #s 1, 2, 5, and 6
Global Early Clock Input to Output Delay for BUFGE #s 3, 4, 7, and 8
Capacitive Load Factor
Figure 1
shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 1
is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Figure 1: Delay Factor at Various Capacitive Loads
Speed Grade
Description
Global Clock Signal Input to Output Delay using
Global Early (GE) clock buffer to clock Output
Flip-Flop for BUFGE #s 1, 2, 5, & 6.
All
Min
0.8
0.8
0.8
0.8
0.9
0.9
0.9
0.9
-09
Max
4.9
5.1
5.3
5.6
5.9
6.2
6.5
6.9
Preliminary
-08
Max
4.4
4.6
4.8
5.1
5.3
5.6
5.9
6.2
-07
Max
3.9
4.1
4.3
4.5
4.8
5.0
5.3
5.6
Units
Symbol
T
ICKEOF
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
ns
ns
ns
ns
ns
ns
ns
ns
Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 1
.
Speed Grade
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
All
Min
1.1
1.1
1.2
1.3
1.3
1.4
1.5
1.6
-09
Max
5.7
5.9
6.1
6.3
6.5
6.8
7.0
7.5
Preliminary
-08
Max
5.1
5.3
5.4
5.6
5.8
6.0
6.3
6.7
-07
Max
4.5
4.7
4.9
5.0
5.2
5.4
5.6
6.0
Units
Description
Symbol
T
ICKEOF
Global Clock Signal Input to Output Delay using
Global Early (GE) clock buffer to clock Output
Flip-Flop for BUFGE #s 3, 4, 7, & 8.
ns
ns
ns
ns
ns
ns
ns
ns
Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 1
.
X8257
-2
0
20
40
Capacitance (pF)
60
80
D
100
120
140
-1
0
1
2
3
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