參數(shù)資料
型號(hào)： XC4028XLA
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 8/16頁(yè)
文件大?。?/td> 72K
代理商： XC4028XLA
R
XC4000XLA/XV FIeld Programmable Gate Arrays
6-178
DS004 (v. 1.3) October 4, 1999 - Product Specification
XC4000XLA Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% func-
tionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaran-
teed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values
for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflect-
ing the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development Sys-
tem) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the
static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay
FastCLK Input to Output Delay for BUFNW, BUFSW, BUFNE, & BUFSE
Speed Grade
Description
Global Low Skew (GLS) Clock Input to Output Delay us-
ing Output Flip-Flop
All
Min
1.2
1.3
1.4
1.4
1.5
1.6
1.6
1.6
0.5
-09
Max
5.6
5.8
6.1
6.4
6.8
7.1
7.4
8.2
1.7
-08
Max
5.0
5.2
5.5
5.7
6.0
6.3
6.6
7.3
1.6
-07
Max
4.5
4.7
4.9
5.1
5.4
5.7
5.9
6.5
1.4
Units
Symbol
T
ICKOF
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
All Devices
ns
ns
ns
ns
ns
ns
ns
ns
ns
For output SLOW option add
T
SLOW
Preliminary
Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 1
.
Speed Grade
Description
FastCLK Input to Output Delay using Output Flip-Flop
for FastCLK buffers BUFNW, BUFSW, BUFNE, and
BUFSE.
All
Min
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
-09
Max
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.4
Preliminary
-08
Max
4.1
4.2
4.3
4.4
4.4
4.5
4.6
4.8
-07
Max
3.7
3.7
3.8
3.9
4.0
4.1
4.1
4.3
Units
Symbol
T
ICKFOF
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
ns
ns
ns
ns
ns
ns
ns
ns
Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 1
.
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