- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374999 > XC4028XLA (Xilinx, Inc.) Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-175
XC4000XLA/XV FIeld Programmable Gate Arrays
6
XC4000XLA CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XLA devices and expressed in nanoseconds unless otherwise noted
CLB Switching Characteristic Guidelines
Speed Grade
-09
-08
-07
Units
Description
Symbol
Min
Max
Min
Max
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
to C
, bypass function generators
Carry Net Delay, C
OUT
to C
IN
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
Hold Time after Clock K
All Hold Times
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control)
T
ILO
T
IHO
T
ITO
T
HH0O
T
HH1O
T
HH2O
T
CBYP
1.1
1.9
2.0
1.7
1.6
1.7
1.1
1.0
1.7
1.8
1.6
1.4
1.6
1.0
0.9
1.5
1.6
1.4
1.3
1.4
0.9
ns
ns
ns
ns
ns
ns
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
NET
1.0
1.2
0.8
1.7
0.1
0.17
0.9
1.1
0.7
1.5
0.1
0.15
0.8
1.0
0.6
1.3
0.1
0.13
ns
ns
ns
ns
ns
ns
T
CKO
T
CKLO
1.5
1.5
1.3
1.3
1.2
1.2
ns
ns
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
0.7
1.4
1.3
1.2
1.3
0.6
0.7
0.5
1.2
2.0
0.7
1.3
1.2
1.1
1.2
0.6
0.6
0.4
1.1
1.7
0.6
1.2
1.1
1.0
1.1
0.5
0.5
0.4
1.0
1.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.0
0.0
0.0
ns
T
CH
T
CL
2.2
2.2
1.9
1.9
1.7
1.7
ns
ns
T
RPW
T
RIO
2.3
2.5
2.3
2.2
2.3
2.0
ns
ns
T
MRW
T
MRQ
F
TOG
12.8
11.4
10.2
ns
See page
184
for TRRI values per device.
227
Preliminary
263
294
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4044XLA-08HQ240I | XC4000XLA/XV Field Programmable Gate Arrays |
| XC4044XL | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4044XLA | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40250XV | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40150XV | XC4000XLA/XV Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4028XLA-07HQ240C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0314 | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0716 | 制造商:Xilinx 功能描述: |
| XC4028XLA08HQ208C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08HQ208C | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。