- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374999 > XC4028XLA (Xilinx, Inc.) Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
XC4000XLA/XV FIeld Programmable Gate Arrays
6-184
DS004 (v. 1.3) October 4, 1999 - Product Specification
IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
IOB Input Delay Guidelines
Speed Grade
Description
-09
-08
-07
Units
Symbol
Device
Min
Max
Min
Max
Min
Max
Clocks
Clock Enable (EC) to Clock (IK)
Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge
Setup Times
Pad to Clock (IK), no delay
T
ECIK
T
OKIK
All devices
All Devices
0.0
1.4
0.0
1.3
0.0
1.2
ns
ns
T
PICK
All Devices
1.2
1.0
0.9
ns
Pad to Clock (IK), via transparent Fast Capture
Latch, no delay
Pad to Fast Capture Latch Enable (OK), no de-
lay
Hold Times
All Hold Times
Global Set/Reset
Minimum GSR Pulse Width
Global Set/Reset
Delay from GSR input to any Q
T
PICKF
All Devices
1.6
1.4
1.3
ns
T
POCK
All Devices
0.8
0.7
0.6
ns
All Devices
0.0
0.0
0.0
ns
T
MRW
All devices
12.8
11.4
10.2
ns
T
RRI*
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
10.2
11.9
12.8
14.5
16.2
17.4
18.7
22.1
9.1
10.6
11.4
12.9
14.4
15.6
16.7
19.7
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no de-
lay
Pad to I1, I2 via transparent FCL and input
latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
T
PID
T
PLI
All devices
All devices
1.0
2.1
0.9
1.9
0.8
1.7
ns
ns
T
PFLI
All devices
2.5
2.2
2.0
ns
T
IKRI
T
IKLI
T
OKLI
All devices
All devices
All devices
1.1
1.2
2.4
1.0
1.1
2.1
0.9
1.0
1.9
ns
ns
ns
Preliminary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4044XLA-08HQ240I | XC4000XLA/XV Field Programmable Gate Arrays |
| XC4044XL | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4044XLA | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40250XV | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40150XV | XC4000XLA/XV Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4028XLA-07HQ240C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0314 | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0716 | 制造商:Xilinx 功能描述: |
| XC4028XLA08HQ208C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08HQ208C | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。