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參數(shù)資料
| 型號(hào)： | XC4028XL-1HQ160I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | FPGA, 1024 CLBS, 18000 GATES, 200 MHz, PQFP160 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 21K |
| 代理商： | XC4028XL-1HQ160I |
2
XC4000E Logic Cell Array Family
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
input,which through configuration can be activated indi-
vidually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This makes the IOBs more versatile, and avoids the
need for clock gating.
Output Drivers
The output pull-up structure can be globally configured to
be either a TTL-like totem-pole (n-channel pull-up transis-
tor, pulling to a voltage one threshold below Vcc, just like
XC4000) or to be CMOS (p-channel pull-up transistor
pulling to Vcc). Also, the configurable pull-up resistor in
XC4000E is a p-channel transistor that pulls to Vcc,
whereas in XC4000 it is an n-channel transistor that pulls
to a voltage one threshold below Vcc.
Input Thresholds
The input thresholds can be globally configured for either
TTL ( 1.2 V threshold) or CMOS ( 2.5 V threshold ), just like
XC2000 and XC3000 inputs. Note that the two global
adjustments of input threshold and output level are inde-
pendent of each other.
Global Signal Access to Logic
There is additional access from global clocks to the F and
G function generator inputs.
Mode-Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
M2, have weak pull-up resistors. For the most popular
configuration mode, Slave Serial, the mode pins can thus
be left unconnected.
For user mode, the three mode inputs can individually be
configured with or without weak pull-up or pull-down
resistors
The PROGRAM input pin has a permanent weak pull-up.
Soft Startup
Like XC3000A, the XC4000E family has “Soft Startup”.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This avoids the potential
ground bounce when all outputs are turned on simulta-
neously. After start-up, the slew rate of the individual
outputs is, as in the XC4000 family, determined by the
individual configuration option.
XC4000E compared to XC4000
Any XC4000E device is a 100% compatible superset of the
equivalent XC4000 device, not only functionally, but also
electrically, and in pin-out and configuration bitstream.
The XC4000E devices have the following additional func-
tions, most of which are invoked through options in the
configuration bitstream:
Synchronous RAM
The two RAMs in any CLB can be changed to synchronous
write operation. In this synchronous mode, the internal
write operation is controlled by the same clock that drives
the flip-flops. The clock polarity is programmable for the
RAM (both F and G function generators together), but is
independent of the chosen flip-flop polarity. Address,
Data, and WE inputs are latched by this rising or falling
clock edge, and a short internal write pulse is generated
right after the clock edge. This self-timed write operation is
thus effectively edge-triggered.
The read operation is not affected by this change to a
synchronous write.
Dual-Port RAM
A separate option converts the 16 x 2 RAM in any CLB into
a 16 x 1 dual-port RAM. In this mode, any operation that
writes into the F-RAM, automatically also writes into the G-
RAM, using the F address. The G-address can, therefore,
not be used to write into the G-RAM.
The CLB can thus be used as an asymmetrical dual-port
RAM, with F being the read address for the F-RAM and the
write address for both F- and G-RAM, while G is the read
address for the G-RAM. Note that F and G can still be
independent read addresses, as they are in XC4000. The
two RAMs together have one read/write port using the F
address, and one read-only port using the G address.
Each CLB can be configured as function generators either
asynchronous single-port, synchronous single-port, or
synchronous dual-port.
H-Function Generator
In XC4000E, the H function generator is more versatile. Its
inputs can come not only from the F and G function
generators but also from up to three control input lines.
The H function generator can be totally or partially inde-
pendent of the other two function generators.
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| XC4028XL-1HQ208C0907 | 制造商:Xilinx 功能描述: |
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| XC4028XL-1HQ240C | 功能描述:IC FPGA C-TEMP 3.3V 1SPD 240HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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