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參數(shù)資料
| 型號： | XC4013E-6HG240M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Programmable Gate Arrays |
| 中文描述： | 可編程門陣列 |
| 文件頁數(shù)： | 61/68頁 |
| 文件大?。?/td> | 462K |
| 代理商： | XC4013E-6HG240M |
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R
May 14, 1999 (Version 1.6)
6-65
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
0
DOUT
CCLK
1
2
3
4
5
6
7
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
RDY/BUSY
INIT
1
0
X6096
Description
Symbol
T
IC
T
DC
T
CD
T
CCH
T
CCL
F
CC
Min
5
60
0
50
60
Max
Units
μ
s
ns
ns
ns
ns
MHz
CCLK
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
8
Notes:
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first
data byte on the
second
rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013E-6HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6HQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6HQ240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6MQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6MQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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