參數(shù)資料
型號: XC4013E-6HG240I
廠商: Xilinx, Inc.
英文描述: Programmable Gate Arrays
中文描述: 可編程門陣列
文件頁數(shù): 53/68頁
文件大?。?/td> 462K
代理商: XC4013E-6HG240I
R
May 14, 1999 (Version 1.6)
6-57
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E/EX/XL Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1:
Note 2:
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
Note 1:
Note 2:
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
RTRC
T
RCRT
T
RCRT
T
2
2
RCL
T
4
RCRR
T
6
RCH
T
5
RCRD
T
7
DUMMY
DUMMY
rdbk.DATA
rdbk.RIP
rdclk.I
rdbk.TRIG
Finished
Internal Net
VALID
X1790
VALID
1
RTRC
T
1
E/EX
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Symbol
Min
200
50
-
-
250
250
Max
-
-
250
250
500
500
Units
ns
ns
ns
ns
ns
ns
rdbk.TRIG
1
2
7
6
5
4
T
RTRC
T
RCRT
T
RCRD
T
RCRR
T
RCH
T
RCL
rdclk.1
XL
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Symbol
Min
200
50
-
-
250
250
Max
-
-
250
250
500
500
Units
ns
ns
ns
ns
ns
ns
rdbk.TRIG
1
2
7
6
5
4
T
RTRC
T
RCRT
T
RCRD
T
RCRR
T
RCH
T
RCL
rdclk.1
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