參數(shù)資料
型號(hào)： XC4013E-6HG240C
廠商： Xilinx, Inc.
英文描述： Programmable Gate Arrays
中文描述： 可編程門陣列
文件頁(yè)數(shù)： 46/68頁(yè)
文件大?。?/td> 462K
代理商： XC4013E-6HG240C
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-50
May 14, 1999 (Version 1.6)
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
There are four major steps in the XC4000 Series power-up
configuration sequence.
Configuration Memory Clear
Initialization
Configuration
Start-Up
The full process is illustrated in
Figure 46
.
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when re-configuring an FPGA by pulsing the PROGRAM
pin
0
X2
2
3
4
5
6
7
8
9 10 11 12 13 14
1
X15
X16
15
SERIAL DATA IN
1
0 15 14 13 12 11 10 9
8
7
6
5
1
1
1
1
CRC – CHECKSUM
LAST DATA FRAME
S
X1789
Polynomial: X16 + X15 + X2 + 1
Readback Data Stream
Figure 45: Circuit for Generating CRC-16
INIT
High if
Master
Sample
Mode Lines
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
V
>3.5 V
No
Yes
Yes
No
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3
μ
s per Frame
Master Waits 50 to 250
μ
s
Before Sampling Mode Lines
Master CCLK
Goes Active
F
Pull INIT Low
and Stop
X6076
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration Memory
Once More
L
Boundary Scan
Instructions
Available:
I
Keep Clearing
Configuration Memory
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
No
Yes
Yes
Figure 46: Power-up Configuration Sequence
相關(guān)PDF資料
PDF描述
XC4013E-6HG240I Programmable Gate Arrays
XC4013E-6HG240M Programmable Gate Arrays
XC4025 Logic Cell Array Family
XC4003 Logic Cell Array Family
XC4003H Logic Cell Array Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4013E-6HG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-6HG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-6HQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E-6HQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E-6HQ240M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
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