參數(shù)資料
型號(hào)： XC4013E-6HG240C
廠商： Xilinx, Inc.
英文描述： Programmable Gate Arrays
中文描述： 可編程門(mén)陣列
文件頁(yè)數(shù)： 16/68頁(yè)
文件大小： 462K
代理商： XC4013E-6HG240C
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-20
May 14, 1999 (Version 1.6)
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 15
shows a simplified block diagram of the
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in
Figure 40 on page 43
, in the “Boundary Scan” section.
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplified block diagram found in
Figure 16
, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
IOB Input Signals
Two paths, labeled I1 and I2 in
Figure 15
and
Figure 16
,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered flip-flop or a level-sensitive latch.
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the XACT Libraries
Guide
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000 Series device inputs are
shown in
Table 8
.
0
1
0
1
M
M
0
1
0
1
M
0
1
M
1
0
M
M
0
3
1
M
M
I
G1
G4
F2
F1
F3
C
OUT
G2
G3
F4
C
INUP
C
IN DOWN
X2000
TO
FUNCTION
GENERATORS
M
M
M
C
OUT0
Figure 14: Detail of XC4000E Dedicated Carry Logic
相關(guān)PDF資料
PDF描述
XC4013E-6HG240I Programmable Gate Arrays
XC4013E-6HG240M Programmable Gate Arrays
XC4025 Logic Cell Array Family
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XC4003H Logic Cell Array Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4013E-6HG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-6HG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-6HQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E-6HQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E-6HQ240M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
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