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| 型號： | XC4013E-4HG240M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Programmable Gate Arrays |
| 中文描述： | 可編程門陣列 |
| 文件頁數(shù)： | 41/68頁 |
| 文件大?。?/td> | 462K |
| 代理商： | XC4013E-4HG240M |
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R
May 14, 1999 (Version 1.6)
6-45
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Table 17: Boundary Scan Instructions
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low—don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “Boundary Scan in
XC4000E Devices“
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
operation
of
the
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACTstep
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
internal
blocks
and
their
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACTstepdevelopment sys-
tem does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k
.) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 4.7 k
is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Instruction I2
I1 I0
0
0
0
0
Test
Selected
EXTEST
SAMPLE/PR
ELOAD
USER 1
TDO Source
I/O Data
Source
DR
Pin/Logic
0
1
DR
DR
0
1
0
BSCAN.
TDO1
BSCAN.
TDO2
Readback
Data
DOUT
—
Bypass
Register
User Logic
0
1
1
USER 2
User Logic
1
0
0
READBACK
Pin/Logic
1
1
1
0
1
1
1
0
1
CONFIGURE
Reserved
BYPASS
Disabled
—
—
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
(TDI end)
X6075
Figure 42: Boundary Scan Bit Sequence
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
X2675
Figure 43: Boundary Scan Schematic Example
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| XC4013E-4HQ240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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