參數(shù)資料
型號: XC4013E-4HG240I
廠商: Xilinx, Inc.
英文描述: Programmable Gate Arrays
中文描述: 可編程門陣列
文件頁數(shù): 56/68頁
文件大?。?/td> 462K
代理商: XC4013E-4HG240I
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-60
May 14, 1999 (Version 1.6)
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 51
shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
Figure 52: Slave Serial Mode Programming Switching Characteristics
XC4000E/X
MASTER
SERIAL
XC4000E/X,
XC5200
SLAVE
XC3100A
SLAVE
XC1700D
PROGRAM
NOTE
:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE
:
M2, M1, M0 can be shorted
to V
CC
if not used as I/O
M2
M0 M1
DOUT
CCLK
CLK
V
CC
+5 V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
INIT
DONE
PROGRAM
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
DOUT
M2
M0 M1
M1
PWRDN
M0
M2
(Low Reset Option Used)
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
4.7 K
V
CC
X9025
N/C
N/C
Figure 51: Master/Slave Serial Mode Circuit Diagram
4 T
CCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
20
0
Max
Units
ns
ns
ns
ns
ns
MHz
CCLK
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
T
DCC
T
CCD
T
CCO
T
CCH
T
CCL
F
CC
30
45
45
10
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
相關(guān)PDF資料
PDF描述
XC4013E-4HG240M Programmable Gate Arrays
XC4013E-5HG240C Programmable Gate Arrays
XC4013E-5HG240I Programmable Gate Arrays
XC4013E-5HG240M Programmable Gate Arrays
XC4013E-6HG240C Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4013E-4HG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-4HQ208C 功能描述:IC FPGA C-TEMP 5V 4SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4013E-4HQ208I 功能描述:IC FPGA I-TEMP 5V 4SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4013E-4HQ240C 功能描述:IC FPGA C-TEMP 5V 4SPD 240-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4013E-4HQ240I 功能描述:IC FPGA I-TEMP 5V 4SPD 240-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱:122-1789