- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374999 > XC4013E-2HG240C (Xilinx, Inc.) Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | XC4013E-2HG240C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Programmable Gate Arrays |
| 中文描述： | 可編程門陣列 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大小： | 462K |
| 代理商： | XC4013E-2HG240C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
R
May 14, 1999 (Version 1.6)
6-41
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 k
- 10 k
external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300
μ
s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
FourSecondaryGlobalinputseach driveadedicated internalglobal netwithshortdelay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
must share an input signal. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal
to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast
Clock buffers serve the two IOB octants on the left side of the die and the other two Fast
Clock buffers serve the two IOB octants on the right side of the die. On each side of the
die,oneFastClockbufferservestheupperoctantandtheotherservestheloweroctant.
If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.
HDC
O
I/O
LDC
O
I/O
INIT
I/O
I/O
PGCK1 -
PGCK4
(XC4000E
only)
Weak
Pull-up
I or I/O
SGCK1 -
SGCK4
(XC4000E
only)
Weak
Pull-up
I or I/O
GCK1 -
GCK8
(XC4000X
only)
Weak
Pull-up
I or I/O
FCLK1 -
FCLK4
(XC4000XLA
and
XC4000XV
only)
Weak
Pull-up
I or I/O
Table 16: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O
After
Config.
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4013E-2HG240I | Programmable Gate Arrays |
| XC4013E-2HG240M | Programmable Gate Arrays |
| XC4013E-3HG240C | Programmable Gate Arrays |
| XC4013E-3HG240I | Programmable Gate Arrays |
| XC4013E-3HG240M | Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013E-2HG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HG240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-2HQ208C | 功能描述:IC FPGA C-TEMP 5V 2SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013E-2HQ208I | 功能描述:IC FPGA I-TEMP 5V 2SPD 208-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013E-2HQ240C | 功能描述:IC FPGA C-TEMP 5V 2SPD 240-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。