參數(shù)資料
型號(hào)： XC4013E-1HG240M
廠商： Xilinx, Inc.
英文描述： Programmable Gate Arrays
中文描述： 可編程門陣列
文件頁(yè)數(shù)： 45/68頁(yè)
文件大?。?/td> 462K
代理商： XC4013E-1HG240M
R
May 14, 1999 (Version 1.6)
6-49
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Notes:
1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value
must
be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in
Table 19
. If a frame data
error is detected during the loading of the FPGA, the con-
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in
Figure 45
. The checksum consists of the 11 most signif-
icant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
Table 20: XC4000E Program Data
Device
XC4003E
3,000
100
(10 x 10)
80
360
126
428
53,936
53,984
XC4005E
5,000
196
(14 x 14)
112
616
166
572
94,960
95,008
XC4006E
6,000
256
(16 x 16)
128
768
186
644
119,792
119,840
XC4008E
8,000
324
(18 x 18)
144
936
206
716
147,504
147,552
XC4010E
10,000
400
(20 x 20)
160
1,120
226
788
178,096
178,144
XC4013E
13,000
576
(24 x 24)
192
1,536
266
932
247,920
247,968
XC4020E
20,000
784
(28 x 28)
224
2,016
306
1,076
329,264
329,312
XC4025E
25,000
1,024
(32 x 32)
256
2,560
346
1,220
422,128
422,176
Max Logic Gates
CLBs
(Row x Col.)
IOBs
Flip-Flops
Bits per Frame
Frames
Program Data
PROM Size
(bits)
Table 21: XC4000EX/XL Program Data
Device
XC4002XL XC4005
2,000
XC4010
10,000
XC4013
13,000
XC4020
20,000
XC4028
28,000
XC4036
36,000
XC4044
44,000
XC4052
52,000
XC4062
62,000
XC4085
85,000
Max Logic
Gates
CLBs
(Row x
Column)
IOBs
Flip-Flops
Bits per
Frame
Frames
Program Data
PROM Size
(bits)
Notes:
5,000
64
(8 x 8)
196
(14 x 14)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
1,024
(32 x 32)
1,296
(36 x 36)
1,600
(40 x 40)
1,936
(44 x 44)
2,304
(48 x 48)
3,136
(56 x 56)
64
256
133
112
616
205
160
1,120
277
192
1,536
325
224
2,016
373
256
2,560
421
288
3,168
469
320
3,840
517
352
4,576
565
384
5,376
613
448
7,168
709
459
61,052
61,104
741
1,023
283,376
283,424
1,211
393,580
393,632
1,399
521,832
521,880
1,587
668,124
668,172
1,775
832,480
832,528
1,963
1,014,876 1,215,320 1,433,804 1,924,940
1,014,924 1,215,368 1,433,852 1,924,992
2,151
2,339
2,715
151,910
151,960
1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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XC4013E-1HQ240I 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E-1HQ240M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
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