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參數(shù)資料
| 型號： | XC40110XV |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000XLA/XV Field Programmable Gate Arrays |
| 中文描述： | XC4000XLA/XV現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 142K |
| 代理商： | XC40110XV |
R
DS015 (v1.3) October 18, 1999 - Product Specification
6-159
XC4000XLA/XV Field Programmable Gate Arrays
6
Three-State Register
XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can significantly improve
output enable and disable time.
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast-
CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.
XLA/XV Power Requirements
XC4000XLA devices require 40% less power per CLB than
equivalent XL devices. XC4000XV devices require 42%
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
the following families can be found in
Table 2
. The K-Factor
predicts device current for typical user designs and is
based on filling the FPGA with active 16-Bit counters and
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:
P=V*K*N*F; where:
P= Device Power
V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members.
Table 3
illustrates the perfor-
mance of the XLA devices. For details regarding the imple-
mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.
Table 2: K-Factor and Relative Power.
FPGA Family
XC4000XL
XC4000XLA
XC4000XV
K-Factor
28
17
13
Power
RelativeTo
XL
1.00
0.60
0.35
Power
RelativeTo
XLA
1.65
1.00
0.58
Table 3: XLA/XV Estimated Benchmark Performance
Register - Register
Benchmarks
Size
Maximum
Frequency
172 MHz
144 MHz
108 MHz
94 MHz
57 MHz
314 MHz
193 MHz
108 MHz
75 MHz
325 MHz
260 MHz
185 MHz
108 MHz
81 MHz
172 MHz
172 MHz
Adder
8-Bit
16-Bit
32-Bit
16-Bit
16-Bit
1 Level
2 Level
4 Level
6 Level
1 CLBs
4 CLBs
16 CLBs
64 CLBs
128 CLBs
8-Bits by 16
8-Bits by 256
2 Cascaded Adders
4 Cascaded Adders
Cascaded 4LUTs
Interconnect
(Manhattan Distance)
Dual Port RAM
(Pipelined)
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