參數(shù)資料
型號(hào)： XC4008
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Family
中文描述： 邏輯單元陣列系列
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 219K
代理商： XC4008
2-54
XC4000 Logic Cell Array Family
Write Operation
Address write cycle time
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
T
WC
T
WCT
T
WP
T
WPT
T
AS
T
AST
T
AH
T
AHT
T
DS
T
DST
T
DHT
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Read Operation
Address read cycle time
16 x 2
32 x 1
16 x 2
32 x 1
T
RC
T
RCT
T
ILO
T
IHO
7.0
10.0
5.5
7.5
5.0
7.0
ns
ns
ns
ns
Data valid after address change
(no Write Enable)
6.0
8.0
4.5
7.0
4.0
6.0
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16 x 2
32 x 1
T
ICK
T
IHCK
6.0
8.0
4.5
6.0
4.5
6.0
ns
ns
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
16 x 2
32 x 1
16 x 2
32 x 1
T
WO
T
WOT
T
DO
T
DOT
12.0
15.0
11.0
14.0
10.0
12.0
9.0
11.0
9.0
11.0
8.5
11.0
ns
ns
ns
ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16 x 2
32 x 1
16 x 2
32 x 1
T
WCK
T
WCKT
T
DCK
T
DCKT
12.0
15.0
11.0
14.0
10.0
12.0
9.0
11.0
9.5
11.5
9.0
11.0
ns
ns
ns
ns
Data setup time before clock K
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Speed Grade
-6
-5
-4
Description
Symbol
Min
Max
Min Max
Min Max Units
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
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