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參數(shù)資料
| 型號： | XC4006 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 219K |
| 代理商： | XC4006 |
2-51
Pad to I1, I2
via transparent
latch, with delay
XC4003 17.6 ns
XC4005 17.9 ns
XC4006 18.0 ns
XC4008 18.3 ns
XC4010 18.6 ns
XC4013 19.3 ns
XC4025 23.5 ns
See page 2-52
T
PDLI
for -4 Speed Grade
Input set-up time
pad to clock (IK)
with delay
XC4003 15.6 ns
XC4005 15.9 ns
XC4006 16.0 ns
XC4008 16.3 ns
XC4010 16.6 ns
XC4013 17.3 ns
XC4025 22.5 ns
T
PICKD
for -4 Speed Grade
X6082
Speed Grade
-6
-5
-4
Description
Symbol
Device
Units
Global Clock to Output (fast) using OFF
T
ICKOF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
15.1
15.5
15.7
16.1
16.5
17.5
25.5
19.9
20.5
20.7
21.1
21.5
22.5
29.5
2.4
2.0
1.8
1.4
1.0
0.5
0
5.1
5.5
5.7
6.1
6.5
7.5
18.0
21.5
21.0
20.8
20.4
20.0
19.0
18.0
0
0
0
0
0
0
0
12.5
13.0
13.2
13.6
14.0
15.0
22.0
15.2
16.0
16.2
16.6
17.0
18.0
25.0
2.0
1.5
1.3
0.9
0.5
0
0
4.0
4.5
4.7
5.1
5.5
6.5
16.0
18.5
18.0
17.8
17.4
17.0
16.0
15.0
0
0
0
0
0
0
0
11.6
12.0
12.2
12.6
13.0
14.0
21.0
14.4
15.0
15.2
15.6
16.0
17.0
24.0
1.6
1.2
1.0
0.6
0.2
0
0
4.0
4.5
4.7
5.1
5.5
6.5
15.5
12.0
12.0
12.0
12.0
12.0
12.0
12.0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Max)
Global Clock to Output (slew limited) using OFF
T
ICKO
(Max)
Input Set-up Time, using IFF (no delay)
T
PSUF
(Min)
Input Hold time, using IFF (no delay)
T
PHF
(Min)
Input Set-up Time, using IFF (with delay)
T
PSU
(Min)
Input Hold Time, using IFF (with delay)
T
PH
(Min)
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the values listed below should be used, and the derived values must be ignored.
OFF
Global Clock-to-Output Delay
.
X3202
T
PG
OFF
Global Clock-to-Output Delay
.
X3202
T
PG
IFF
Input
Set-Up
&
Hold
Time
X3201
D
T
PG
IFF
Input
Set-Up
&
Hold
Time
X3201
D
T
PG
IFF
Input
Set-Up
&
Hold
Time
X3201
D
T
PG
IFF
Input
Set-Up
&
Hold
Time
X3201
D
T
PG
Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). When testing fast outputs, only one
output switches. When testing slew-rate limited outputs, half the number of outputs on one side of the device are switching. These
parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the most
unfavorable clock polarity choice.
PRELIMINARY
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