參數(shù)資料
型號(hào)： XC4003H
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Families
中文描述： 家庭邏輯單元陣列
文件頁(yè)數(shù)： 2/22頁(yè)
文件大?。?/td> 219K
代理商： XC4003H
2-48
XC4000 Logic Cell Array Family
Absolute Maximum Ratings
Symbol
Description
Units
V
CC
Supply voltage relative to GND
–0.5 to +7.0
V
V
IN
Input voltage with respect to GND
–0.5 to V
CC
+0.5
V
V
TS
Voltage applied to 3-state output
–0.5 to V
CC
+0.5
V
T
STG
Storage temperature (ambient)
–65 to + 150
°
C
T
SOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+ 260
°
C
T
J
Junction temperature
+ 150
°
C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Description
Min
Max
Units
V
CC
Supply voltage relative to GND Commercial 0
°
C to 85
°
C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40
°
C to 100
°
C junction
4.5
5.5
V
Supply voltage relative to GND
Military –55
°
C to 125
°
C case
4.5
5.5
V
V
IH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0
V
CC
V
V
IL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
0.8 V
T
IN
Input signal transition time
250
ns
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
Units
V
OH
High-level output voltage @ I
OH
= –4.0 mA, V
CC
min
2.4
V
V
OL
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min (Note 1)
0.4
V
I
CCO
Quiescent LCA supply current (Note 2)
10
mA
I
IL
Leakage current
–10
+10
μ
A
C
IN
Input capacitance (sample tested)
15
pF
I
RIN
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
0.02
0.25
mA
I
RLL
Horizontal Long Line pull-up (when selected) @ logic Low
0.2
2.5
mA
Note: 1. With 50% of the outputs simultaneously sinking 12 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at V
CC
or GND, and
the LCA configured with a MakeBits tie option.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°
C.
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