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參數(shù)資料
| 型號： | XC4002XL-6PQ100M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | XC4000E和XC4000X系列現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 21K |
| 代理商： | XC4002XL-6PQ100M |
3
Speed Grade
-4
-3
-2
Description
Symbol
Min
Max
Min Max
Min Max Units
Input
Propagation Delays
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
T
PID
T
PLI
T
PDLI
T
IKRI
T
IKLI
2.5
3.6
7.1
2.8
3.0
ns
ns
ns
ns
ns
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
T
PICK
T
PICKD
4.7
8.3
ns
ns
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
T
IKPI
T
IKPID
0
0
ns
ns
Output
Propagation Delays
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
T
OKPOF
T
OKPOS
T
OPF
T
OPS
T
TSHZ
T
TSONF
T
TSONS
4.6
11.2
5.8
12.4
4.2
8.1
14.7
ns
ns
ns
ns
ns
ns
ns
(slew -rate limited)
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
T
OOK
T
OKO
3.7
0
ns
ns
Clock
Clock High or Low time
T
CH/
T
CL
4.0
ns
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width
*
T
RRI
T
RPO
T
MRW
7.2
ns
ns
ns
18.9
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
* Timing is based on the XC4005E. For other devices see XACT timing calculator.
** See preceding page
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
Slew rate limited
output
rise/fall times are approximately two times longer than
fast
output rise/fall times. For the effect of capacitive loads on
ground bounce, see pages 8-8 through 8-10.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the
external system hold time
to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4002XL-6VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4002XL-6VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4002XL-6VQ100M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4003 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC4003-4PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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