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參數(shù)資料
| 型號： | XC3195A-1PP175C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 484 CLBS, 6500 GATES, 323 MHz, PPGA175 |
| 封裝： | PLASTIC, PGA-175 |
| 文件頁數(shù)： | 7/50頁 |
| 文件大小： | 474K |
| 代理商： | XC3195A-1PP175C |
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2-109
Figure 4.
Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has.
five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to com-
pile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
G
F
QX
QY
DIN
G
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
MUX
1
MUX
相關PDF資料 |
PDF描述 |
|---|---|
| XC3195A-1PQ208C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3195A-2PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3195A-2PC84I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3195A-2PG175C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3195A-2PG175I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3195A-1PQ160C | 制造商:Xilinx 功能描述: |
| XC3195A-1PQ208C | 制造商:Xilinx 功能描述: |
| XC3195A-2PC84C | 制造商:Xilinx 功能描述: |
| XC3195A-2PG175C | 制造商:Xilinx 功能描述: |
| XC3195A-2PG223I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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