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參數(shù)資料
| 型號(hào)： | XC3195A-1PG175C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 484 CLBS, 6500 GATES, 323 MHz, CPGA175 |
| 封裝： | CERAMIC, PGA-175 |
| 文件頁數(shù)： | 30/50頁 |
| 文件大小： | 474K |
| 代理商： | XC3195A-1PG175C |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-132
General LCA Switching Characteristics
Description
Symbol
Min
Max
Units
RESET (2)
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
4
T
MR
T
RM
T
MRW
1
3
6
μ
s
μ
s
μ
s
DONE/PROG
Width (Low) required for Re-config.
INIT response after D/P is pulled Low 6
5
T
PGW
T
PGI
6
μ
s
μ
s
7
PWRDWN (3)
Power Down V
CC
V
CCPD
2.3
V
Notes: 1. At power-up, V
cc
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until V
cc
has reached 4.0 V (2.5 V for XC3000L). A very long V
cc
rise time of >100 ms, or
a non-monotonically rising V
cc
may require a >1-
μ
s High level on RESET, followed by a >6-
μ
s Low level on RESET and
D/P after V
cc
has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while V
cc
>4.0 V(2.5 V for XC3000L).
4 T
MRW
2 T
MR
3 T
RM
5 T
PGW
6 T
PGI
Clear State
Configuration State
User State
Note 3
V
CCPD
X5387
RESET
M0/M1/M2
DONE/PROG
INIT
(Output)
PWRDWN
V
CC
(Valid)
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| XC3195A-1PQ160C | 制造商:Xilinx 功能描述: |
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