參數(shù)資料
型號： XC3190A-4PC84C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 320 CLBS, 5000 GATES, 227 MHz, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 5/50頁
文件大?。?/td> 474K
代理商： XC3190A-4PC84C
2-107
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide
programming compatibility for mixes of various LCA device
devices in a synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 3, provides
an interface between the external package pin of the
device and the internal user logic. Each IOB includes both
registered and direct input paths. Each IOB provides a
programmable 3-state output buffer, which may be driven
by a registered or direct output signal. Configuration
options allow each IOB an inversion, a controlled slew rate
and a high impedance pull-up. Each input circuit also
provides input clamping diodes to provide electrostatic
protection, and circuits to inhibit latch-up produced by
input currents.
FLIP
FLOP
Q
D
R
SLEW
RATE
PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
D
Q
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IK
OK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
Figure 3.
Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two
clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that
triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can
only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
Figure 2.
Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.
The memory cell outputs Q and Q use ground and V
levels and provide continuous, direct control. The addi-
tional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory
cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
Q
Data
Read or
Write
Configuration
Control
Q
X5382
相關(guān)PDF資料
PDF描述
XC3190A-4PC84I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PQ160C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PQ160I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PQ208C Field Programmable Gate Arrays
XC3190A-4PQ208I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3190A-4PC84I 制造商:Xilinx 功能描述:
XC3190A-4PG175C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PG175I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PP175C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-4PP175I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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