參數(shù)資料
型號(hào)： XC3190A-3PG175I
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 320 CLBS, 5000 GATES, 270 MHz, CPGA175
封裝： CERAMIC, PGA-175
文件頁(yè)數(shù)： 29/50頁(yè)
文件大?。?/td> 474K
代理商： XC3190A-3PG175I
2-131
Program Readback Switching Characteristics
Description
Symbol
Min
Max
Units
CCLK
To DOUT
3
T
CCO
100
ns
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
1
2
4
5
T
DCC
T
CCD
T
CCH
T
CCL
F
CC
60
0
ns
ns
μ
s
μ
s
MHz
0.05
0.05
5.0
10
Slave Serial Mode Programming Switching Characteristics
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the INIT of all LCA devices is High.
3. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of >100
ms, or a non-monotonically rising V
CC
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level on
RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
Description
RTRIG High
Symbol
Min
250
Max
Units
ns
RTRIG
1
T
RTH
CCLK
RTRIG setup
RDATA delay
High time
Low time
2
3
5
4
T
RTCC
T
CCRD
T
CCHR
T
CCLR
200
ns
ns
μ
s
μ
s
100
0.5
0.5
5
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins.
3. Readback should not be initiated until configuration is complete.
4. T
CCLR
is 5
μ
s min to 15
μ
s max for XC3000L.
4 T
CCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379
1 T
RTH
5
3
4
4
2
T
CCL
T
CCRD
T
CCL
T
RTCC
DONE/PROG
(OUTPUT)
X6116
RTRIG (M0)
CCLK(1)
VALID
READBACK OUTPUT
H1-Z
VALID
READBACK OUTPUT
M1 Input/
RDATA Output
相關(guān)PDF資料
PDF描述
XC3195A-3PG175I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PP175C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3195A-3PP175C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PP175I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3195A-3PP175I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3190A-3PP175C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PP175I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PQ160C 功能描述:IC LOGIC CL ARRAY 9000GAT 160PQF RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3190A-3PQ160C0262 制造商:Xilinx 功能描述:
XC3190A-3PQ160I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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