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參數(shù)資料
| 型號： | XC3190A-3PG175C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 320 CLBS, 5000 GATES, 270 MHz, CPGA175 |
| 封裝： | CERAMIC, PGA-175 |
| 文件頁數(shù)： | 27/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3190A-3PG175C |
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2-129
Peripheral Mode Programming Switching Characteristics
6
BUSY
T
D6
DOUT
RDY/BUSY
D7
D0
D1
D2
4
WTRB
T
Valid
2
DC
T
1
CA
T
CCLK
D0-D7
CS2
WS, CS0, CS1
3
CD
T
WRITE TO LCA
X3249
Previous Byte
New Byte
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will
go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immedi-
ately after the end of BUSY.
Periods
Description
Symbol
Min
Max
Units
Write
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
1
T
CA
100
ns
DIN Setup time required
DIN Hold time required
2
3
T
DC
T
CD
60
0
ns
ns
RDY/BUSY delay after end of WS
4
T
WTRB
60
ns
RDY
Earliest next WS after end of BUSY
5
T
RBWT
0
ns
BUSY Low time generated
6
T
BUSY
2.5
9
CCLK
Notes:
1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of
>100 ms, or a non-monotonically rising V
CC
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level
on RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T
BUSY
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
T
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
BUSY
occurs when a new
word is loaded into the input register before the second-level buffer has started shifting out data.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3190A-3PG175I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3190A-3PP175C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3190A-3PP175I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3190A-3PQ160C | 功能描述:IC LOGIC CL ARRAY 9000GAT 160PQF RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC3190A-3PQ160C0262 | 制造商:Xilinx 功能描述: |
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