參數(shù)資料
型號(hào)： XC3164A-3TQ144I
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 224 CLBS, 3500 GATES, 270 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 36/50頁
文件大?。?/td> 474K
代理商： XC3164A-3TQ144I
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-138
Configuration Mode <M2:M1:M0>
SLAVE
<1:1:1>
MASTER-SER
<0:0:0>
PERIPHERAL
<1:0:1>
MASTER-HIGH
<1:1:0>
MASTER-LOW
<1:0:0>
***
44
PLCC
7
12
16
17
18
19
20
22
23
26
27
28
30
34
38
39
40
1
X
68
PLCC
10
18
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
X
X
84
PLCC
12
22
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
64
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
1
2
3
4
5
8
9
10
11
X
X
X
X**
X**
X**
84
PGA
B2
F3
J2
L1
K2
K3
L3
K6
J6
L11
K10
J10
K11
J11
H10
F10
G10
G11
F9
F11
E11
E10
D10
C11
B11
C10
A11
B10
B9
A10
A9
B6
B7
A7
C7
C6
A6
A5
B5
C5
A3
A2
B3
A1
X
X
X
100
PQFP
29
41
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
91
92
93
94
98
99
100
1
2
5
6
8
9
12
13
14
15
16
17
18
19
20
23
24
25
26
X
X
X
132
PGA
A1
C8
B13
A14
C13
B14
D14
G14
H12
M13
P14
N13
M12
P13
N11
M9
N9
N8
M8
N7
P6
M6
M5
N4
N2
M3
P1
M2
N1
L2
L1
K1
J2
H1
H2
H3
G2
G1
F2
E1
D1
D2
B1
C2
X
X
160
PQFP
159
20
40
42
44
45
49
59
19
76
78
80
81
82
86
92
93
98
100
102
103
108
114
115
119
120
121
124
125
128
129
132
133
136
137
139
141
142
147
148
151
152
155
156
X
X
175
PGA
B2
D9
B14
B15
C15
E14
D16
H15
J14
P15
R15
R14
N13
T14
P12
T11
R10
R9
N9
P8
R8
R7
R5
P5
R3
N4
R2
P2
M3
P1
N1
M1
L2
K2
K1
J3
H2
H1
F2
E1
D1
C1
E3
C2
X
X
User
Operation
PWRDWN (I)
VCC
RDATA
RTRIG (I)
I/O
I/O
I/O
I/O
GND
XTL2 OR I/O
RESET (I)
PROGRAM (I)
I/O
XTL1 OR I/O
I/O
I/O
I/O
I/O
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
All Others
XC3020 etc.
XC3030 etc.
XC3042 etc.
XC3064 etc.
XC3090 etc.
XC3195
X5266
100
TQFP
26
38
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
88
89
90
91
95
96
97
98
99
2
3
5
6
9
10
11
12
13
14
15
16
17
20
21
22
26
X
X
3
26
48
50
56
57
61
77
79
100
102
107
109
110
115
122
123
128
130
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
182
184
185
192
193
199
200
203
204
X
X
****
208
PQFP
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
VCC
DIN (I)
DOUT
CCLK(O)
GND
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
VCC
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK(O)
A0
A1
A2
A3
A15
A4
A14
A5
GND
A13
A6
A12
A7
A11
A8
A10
A9
PWRDWN (I)
VCC
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
VCC
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK(O)
A0
A1
A2
A3
A15
A4
A14
A5
GND
A13
A6
A12
A7
A11
A8
A10
A9
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
CS0 (I)
DATA 4 (I)
VCC
DATA 3 (I)
CS1 (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK(O)
WS (I)
CS2 (I)
GND
PWRDWN (I)
VCC
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
VCC
DIN (I)
DOUT
CCLK (I)
GND
Pin Functions During Configuration
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with
a 50 k
to 100 k
pull-up resistor.
Represents a 50-k
to 100-k
pull-up before and during configuration
INIT is an open drain output during configuration
Represents an input
Pin assignmnent for the XC3064/XC3090 and XC3195 differ from those shown. See page 2-138.
Peripheral mode and master parallel mode are not supported in the PC44 package. See page 2-135.
Pin assignments for the XC3195 PQ208 differ from those shown. See page 2-146.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not electrically identical.
Generic I/O pins are not shown.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
For a detailed description of the configuration modes, see pages 2-190 through 2-200.
For pinout details, see pages 2-136 through 2-146.
*
(I)
**
***
****
相關(guān)PDF資料
PDF描述
XC3164A-4PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3164A-4PC84I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3164A-4PQ160C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3164A-4PQ160I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3164A-4TQ144C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3164A-4PC84C 制造商:Xilinx 功能描述:XLXXC3164A-4PC84C IC SYSTEM GATE
XC3164A-4PC84I 制造商:Xilinx 功能描述:
XC3164A4PG132AKJ 制造商:XILINX 功能描述:*
XC3164A-4PQ160C 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 224 Cell, 160 Pin, Plastic, QFP
XC3164A-4PQ160I 制造商:Xilinx 功能描述:
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