參數(shù)資料
型號： XC3142A-2PC84C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 323 MHz, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 40/50頁
文件大小： 474K
代理商： XC3142A-2PC84C
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-142
XC3064/XC3090/XC3195 84-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
PLCC
Pin Number
XC3064, XC3090, XC3195
54
55
RESET
DONE-PG
56
57
58
59
60
61
D7-I/O
XTL1(OUT)-BCLKIN-I/O
D6-I/O
I/O
D5-I/O
CS0-I/O
62
63
64
65
66
67
D4-I/O
I/O
VCC
GND
1
D3-I/O
1
CS1-I/O
1
68
69
70
71
D2-I/O
1
I/O
D1-I/O
RDY/BUSY-RCLK-I/O
72
73
74
75
D0-DIN-I/O
DOUT-I/O
CCLK
A0-WS-I/O
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
10
11
A1-CS2-I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
A14-I/O
A5-I/O
GND
VCC
1
A13-I/O
1
A6-I/O
1
A12-I/O
1
A7-I/O
1
I/O
A11-I/O
A8-I/O
A10-I/O
A9-I/O
PLCC
Pin Number XC3064, XC3090, XC3195
12
PWRDN
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TCLKIN-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
1
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
32
33
34
35
36
M0-RTRIG
M2-I/O
HDC-I/O
I/O
LDC-I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
I/O
I/O
I/O
INIT/I/O
1
VCC
1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XTL2(IN)-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
ouptuts are default slew-rate limited.
In the PC84 package, XC3064, XC3090 and XC3195 have additional V
CC
and GND pins and thus a different pin definition than
XC3020/XC3030/XC3042.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3142A-2PC84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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XC3142A-2PQ100C 制造商:Xilinx 功能描述:
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