參數(shù)資料
型號(hào)： XC3120A-4PQ100I
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 64 CLBS, 1000 GATES, 227 MHz, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 27/50頁(yè)
文件大?。?/td> 474K
代理商： XC3120A-4PQ100I
2-129
Peripheral Mode Programming Switching Characteristics
6
BUSY
T
D6
DOUT
RDY/BUSY
D7
D0
D1
D2
4
WTRB
T
Valid
2
DC
T
1
CA
T
CCLK
D0-D7
CS2
WS, CS0, CS1
3
CD
T
WRITE TO LCA
X3249
Previous Byte
New Byte
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will
go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immedi-
ately after the end of BUSY.
Periods
Description
Symbol
Min
Max
Units
Write
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
1
T
CA
100
ns
DIN Setup time required
DIN Hold time required
2
3
T
DC
T
CD
60
0
ns
ns
RDY/BUSY delay after end of WS
4
T
WTRB
60
ns
RDY
Earliest next WS after end of BUSY
5
T
RBWT
0
ns
BUSY Low time generated
6
T
BUSY
2.5
9
CCLK
Notes:
1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of
>100 ms, or a non-monotonically rising V
CC
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level
on RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T
BUSY
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
T
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
BUSY
occurs when a new
word is loaded into the input register before the second-level buffer has started shifting out data.
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