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參數(shù)資料
| 型號： | XC3120A-3PC84C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 64 CLBS, 1000 GATES, 270 MHz, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 23/50頁 |
| 文件大小： | 474K |
| 代理商： | XC3120A-3PC84C |
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2-125
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
T
DSCK
2
T
CKDS
n
n + 1
n + 2
n – 3
n – 2
n – 1
n
X3223
Master Serial Mode Programming Switching Characteristics
Speed Grade
Min
Max
Units
Description
Symbol
CCLK
Data In setup
Data In hold
1
2
T
DSCK
60
0
ns
ns
CKDS
Notes: 1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of
>100 ms, or a non-monotonically rising V
CC
may require >6-
μ
s High level on RESET, followed by a >6-
μ
s Low
level on RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
3. Master-serial-mode timing is based on slave-mode testing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3120A-3PC84I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PQ100I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-4PC68C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-4PC68I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-4PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3120A-3PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-4PC68C | 制造商:Xilinx 功能描述: |
| XC3120A-4PC68I | 制造商:Xilinx 功能描述: |
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