參數(shù)資料
型號： XC3120A-3PC84C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 64 CLBS, 1000 GATES, 270 MHz, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 16/50頁
文件大?。?/td> 474K
代理商： XC3120A-3PC84C
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-118
Table 1
M0 M1 M2 CCLK
Mode
Data
0
0
0
0
0
0
1
1
0
1
0
1
output
output
—
output
Master
Master
reserved
Master
Bit Serial
Byte Wide Addr. = 0000 up
—
Byte Wide Addr. = FFFF
down
—
Peripheral Byte Wide
reserved
—
Slave
Bit Serial
1
1
1
1
0
0
1
1
0
1
0
1
—
output
—
input
reserved
Alternate
Clock Buffer
XTAL1
XTAL2
(IN)
R1
R2
Y1
C1
C2
Internal
External
R1
R2
C1, C2
Y1
Suggested Component Values
0.5 – 1 M
0 – 1 k
(may be required for low frequency, phase)t
(shift and/or compensation level for crystal Q)
10 – 40 pF
1 – 20 MHz AT-cut parallel resonant
X5302
68 PIN
PLCC
47
43
84 PIN
PLCC
57
53
PGA
J11
L11
132 PIN
PGA
P13
M13
160 PIN
PQFP
82
76
XTAL 1 (OUT)
XTAL 2 (IN)
100 PIN
CQFP
67
61
PQFP
82
76
164 PIN
CQFP
105
99
44 PIN
PLCC
30
26
175 PIN
PGA
T14
P15
208 PIN
PQFP
110
100
D
Q
resistance. Crystal oscillators above 20 MHz generally
require a crystal which operates in a third overtone mode,
where the fundamental frequency must be suppressed by
an inductor across C2, turning this parallel resonant circuit
to double the fundamental crystal frequency, i.e., 2/3 of the
desired third harmonic frequency network. When the oscil-
lator inverter is not used, these IOBs and their package
pins are available for general user I/O.
Programming
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vcc reaches the voltage at which portions
of the LCA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-
down mode is inhibited. The Initialization state time-out
(about 11 to 33 ms) is determined by a 14-bit counter
driven by a self-generated internal timer. This nominal 1-
MHz timer is subject to variations with process, tempera-
ture and power supply. As shown in Table 1, five configu-
ration mode choices are available as determined by the
input levels of three mode pins; M0, M1 and M2.
In Master configuration modes, the LCA device becomes
the source of the Configuration Clock (CCLK). The begin-
ning of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An LCA device with mode lines selecting
a Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
Figure 17.
Crystal Oscillator Inverter.
When activated in the MakeBits program and by selecting an output network for its buffer,
the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3120A-3PC84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3120A-3PQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3120A-3PQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3120A-4PC68C 制造商:Xilinx 功能描述:
XC3120A-4PC68I 制造商:Xilinx 功能描述:
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