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參數(shù)資料
| 型號： | XC3120A-2PC68C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 64 CLBS, 1000 GATES, 323 MHz, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3120A-2PC68C |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-112
X2662
Figure 8.
XACT Development System
Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot
pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP that drives from a horizontal to a vertical line.
D:V->H is a PIP that drives from a vertical to a horizontal line.
D:C->T is a “T” PIP that drives from a cross of a T to the tail.
D:CW is a corner PIP that drives in the clockwise direction.
P0 indicates the PIP is non-conducting , P1 is on.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3120A-2PC68I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-2PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-2PC84I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-1PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3164A-1PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3120A-2PC68I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-2PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-2PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-2PG84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3120A-2PQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
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