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參數(shù)資料
| 型號： | XC3064A-7PG132I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 224 CLBS, 4000 GATES, 113 MHz, CPGA132 |
| 封裝： | CERAMIC, PGA-132 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 48K |
| 代理商： | XC3064A-7PG132I |
2-167
Speed Grade
-7
-6
Description
Symbol
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
T
PID
T
PTG
T
IKRI
4.0
15.0
3.0
3.0
14.0
2.5
ns
ns
ns
4
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T
PICK
14.0
12.0
ns
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (fast)
same
3-state to Pad active and valid (fast)
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
7
7
10
10
9
9
8
8
T
OKPO
T
OKPO
T
OPF
T
OPS
T
TSHZ
T
TSHZ
T
TSON
T
TSON
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
7.0
15.0
5.0
13.0
9.0
12.0
10.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
(slew-rate limited)
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
6
T
OOK
T
OKO
8.0
0
7.0
0
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
T
IOH
T
IOL
F
CLK
4.0
4.0
3.5
3.5
ns
ns
MHz
113.0
135.0
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In (Q)
RESET Pad to output pad
13
15
15
T
RRI
T
RPO
T
RPO
24.0
33.0
43.0
23.0
29.0
37.0
ns
ns
ns
(fast)
(slew-rate limited)
IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. T
PID
, T
PTG
, and T
PICK
are 3 ns higher for XTL2 when the pin is configured as a user input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3064A-7PP132C | 制造商:Xilinx 功能描述: |
| XC3064A-7PP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3064A-7PQ160C | 功能描述:IC LOGIC CL ARRAY 6400GAT 160PQF RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3064A7PQ160I | 制造商:XILINX 功能描述:New |
| XC3064A-7PQ160I | 制造商:Xilinx 功能描述:XILINX XC3064A-7PQ160I FPGA - Trays 制造商:Xilinx 功能描述:FPGA XC3000A Family 4.5K Gates 224 Cells 113MHz CMOS Technology 5V 160-Pin PQFP |
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