參數(shù)資料
型號(hào): XC3064A-7PG132I
廠商: XILINX INC
元件分類(lèi): FPGA
英文描述: Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述: FPGA, 224 CLBS, 4000 GATES, 113 MHz, CPGA132
封裝: CERAMIC, PGA-132
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 48K
代理商: XC3064A-7PG132I
2-164
XC3000A Logic Cell Array Family
Speed Grade
-7
-6
Description
Symbol
Max
Max
Units
Global and Alternate Clock Distribution*
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
T
PID
7.5
7.0
ns
T
PIDC
6.0
5.7
ns
TBUF
driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T
to L.L. active and valid with single pull-up resistor
T
to L.L. active and valid with pair of pull-up resistors
T
to L.L. High with single pull-up resistor
T
to L.L. High with pair of pull-up resistors
T
IO
T
ON
T
ON
T
PUS
T
PUF
4.5
9.0
11.0
16.0
10.0
4.0
8.0
10.0
14.0
8.0
ns
ns
ns
ns
ns
BIDI
Bidirectional buffer delay
T
BIDI
1.7
1.5
ns
CLB Switching Characteristic Guidelines
Buffer (Internal) Switching Characteristic Guidelines
* Timing is based on the XC3042A, for other devices see XACT timing calculator.
1
T
ILO
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
8
T
CKO
X5424
13 T
T
RPW
9
T
RIO
4
T
DICK
6
T
ECCK
12 T
CL
2
T
ICK
3
T
CKI
11 T
CH
5
T
CKDI
7
T
CKEC
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