參數(shù)資料
型號(hào)： XC3042L-8TQ144I
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 80 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 33/50頁(yè)
文件大小： 474K
代理商： XC3042L-8TQ144I
2-135
Dynamic Power Consumption
XC3042
XC3042A
XC3042L
XC3142A
One CLB driving three local interconnects
0.25
0.17
0.07
0.25
mW per MHz
One global clock buffer and clock line
2.25
1.40
0.50
1.70
mW per MHz
One device output with a 50 pF load
1.25
1.25
0.55
1.25
mW per MHz
Power Consumption
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any design, the configu-
ration option of TTL chip input threshold requires power for
the threshold reference. The power required by the static
memory cells that hold the configuration data is very low
and may be maintained in a power-down mode.
Typically, most of power dissipation is produced by exter-
nal capacitive loads on the output buffers. This load and
frequency dependent power is 25
μ
W/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an LCA device, the fraction of nodes changing on a
given clock is typically low (10-20%). For example, in a
long binary counter, the total activity of all counter flip-flops
is equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is be-
tween 2.0 mW/MHz for the XC3020 and 3.5 mW/MHz for
the XC3090. The internal capacitive load is more a func-
tion of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
power loss. The Logic Cell Array has built in Powerdown
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their high-impedance state with no pull-ups.
Different from the XC3000 family which can be powered
down to a current consumption of a few microamps, the
XC3100 draws 5 mA, even in power-down. This makes
power-down operation less meaningful. In contrast, I
CCPD
for the XC3000L is only 10
μ
A.
To force the Logic Cell Array into the Powerdown state, the
user must pull the PWRDWN pin Low and continue to
supply a retention voltage to the V
CC
pins. When normal
power is restored, V
CC
is elevated to its normal operating
voltage and PWRDWN is returned to a High. The Logic
Cell Array resumes operation with the same internal se-
quence that occurs at the conclusion of configuration.
Internal-I/O and logic-block storage elements will be reset,
the outputs will become enabled and the DONE/PROG
pin will be released.
When V
CC
is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input
protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and
drive the V
CC
connection. This condition can produce
invalid power conditions and should be avoided. A large
series resistor might be used to limit the current or a bipolar
buffer may be used to isolate the input signal.
相關(guān)PDF資料
PDF描述
XC3142A-4PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142A-4PC84I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142A-4PQ100I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142A-4TQ144C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142A-4TQ144I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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