參數(shù)資料
型號: XC3042L-8TQ144C
廠商: XILINX INC
元件分類: FPGA
英文描述: Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述: FPGA, 144 CLBS, 2000 GATES, 80 MHz, PQFP144
封裝: PLASTIC, TQFP-144
文件頁數(shù): 37/50頁
文件大?。?/td> 474K
代理商: XC3042L-8TQ144C
2-139
Number of Available I/O Pins
64
54
Number of Package Pins
Max I/O
68
58
58
84
64
74
74
70
70
70
100
8
82
120
132
96
110
144
156
160
120
138
164
142
175
144
144
191
196
208
144
176
223
176
240
64
80
96
120
144
176
XC3020/XC3120
XC3030/XC3130
XC3042/XC3142
XC3064/XC3164
XC3090/XC3190
XC3195
64
X3478
44
34
176
144
XC3000 Families Pin Assignments
Xilinx offers the six different array sizes in the XC3000
families in a variety of surface-mount and through-hole
package types, with pin counts from 44 to 223.
Each chip is offered in several package types to accommo-
date the available PC board space and manufacturing
technology. Most package types are also offered with
different chips to accommodate design changes without
the need for PC board changes.
Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
package. In some cases, the chip has more pads than
there are pins on the package, as indicated by the informa-
tion (“unused” pads) below the line in the following table.
The IOBs of the unconnected pads can still be used as
storage elements if the specified propagation delays and
set-up times are acceptable.
In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the
following table.
3020
3030
3042
3064
3090
3195
Device
74
98
118
142
166
198
Pads
54 u
44
34 u
64
6 u
30 u
68
10 n.c.
14 u
34 u
50 u
82 u
114 u
84
26 n.c.
2 n.c.
18 u
100
14 n.c.
10 u
132
26 n.c.
2 u
144
18 n.c.
6 u
160
9 n.c
9 n.c.
32 u
175
10 n.c.
176
42 n.c.
10 n.c.
208
25 n.c.
223
n.c. = Unconnected package pin
u = Unbonded device pad
X6095
Number of Package Pins
Number of Unbounded or Unconnected Pins
相關(guān)PDF資料
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