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參數(shù)資料
| 型號： | XC3042A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | TUBE,SHR,POL,3/16,BLK,600V, (1005230, 828000, 1000892) |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 48K |
| 代理商： | XC3042A |
2-167
Speed Grade
-7
-6
Description
Symbol
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
T
PID
T
PTG
T
IKRI
4.0
15.0
3.0
3.0
14.0
2.5
ns
ns
ns
4
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T
PICK
14.0
12.0
ns
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (fast)
same
3-state to Pad active and valid (fast)
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
7
7
10
10
9
9
8
8
T
OKPO
T
OKPO
T
OPF
T
OPS
T
TSHZ
T
TSHZ
T
TSON
T
TSON
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
7.0
15.0
5.0
13.0
9.0
12.0
10.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
(slew-rate limited)
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
6
T
OOK
T
OKO
8.0
0
7.0
0
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
T
IOH
T
IOL
F
CLK
4.0
4.0
3.5
3.5
ns
ns
MHz
113.0
135.0
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In (Q)
RESET Pad to output pad
13
15
15
T
RRI
T
RPO
T
RPO
24.0
33.0
43.0
23.0
29.0
37.0
ns
ns
ns
(fast)
(slew-rate limited)
IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. T
PID
, T
PTG
, and T
PICK
are 3 ns higher for XTL2 when the pin is configured as a user input.
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