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參數(shù)資料
| 型號： | XC3042A-7PC84I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 113 MHz, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 28/50頁 |
| 文件大小： | 474K |
| 代理商： | XC3042A-7PC84I |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-130
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUT pin. There is an internal delay of 0.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next LCA device in the daisy-chain accepts
data on the subsequent rising CCLK edge.
Figure 24.
Slave Serial Mode.
D/P
RESET
X3157
LCA
General-
Purpose
User I/O
Pins
+5 V
M0
M1
PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
.
Other
I/O Pins
INIT
+5 V
5 k‰
If Readback is
Activated, a
5-k‰ Resistor is
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
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相關代理商/技術參數(shù) |
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| XC3042A-7PC84I0100 | 制造商:Xilinx 功能描述: |
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