參數(shù)資料
型號(hào)： XC3042A-6TQ144C
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 135 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 35/50頁(yè)
文件大?。?/td> 474K
代理商： XC3042A-6TQ144C
2-137
User I/O Pins that can have special functions.
M2
During configuration, this input has a weak pull-up resistor.
Together with M0 and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.
HDC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After con-
figuration, this pin is a user-programmable I/O pin.
LDC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.
INIT
This is an active Low open-drain output with a weak pull-
up and is held Low during the power stabilization and
internal clearing of the configuration memory. It can be
used to indicate status to a configuring microprocessor or,
as a wired AND of several slave mode devices, a hold-off
signal for a master mode device. After configuration this
pin becomes a user-programmable I/O pin.
BCLKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTL1
This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/
O Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.
CS0, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configu-
ration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the D0-
D7 data. In Master-Parallel mode, WS and CS2 are the A0
and A1 outputs. After configuration, these pins are user-
programmable I/O pins.
RDY/BUSY
During Peripheral Parallel mode configuration this pin
indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
RCLK
During Master Parallel mode configuration, each change
on the A0-15 outputs is preceded by a rising edge on
RCLK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed I/O pin.
D0-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed
I/O pins.
A0-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configu-
ration, they are user-programmable I/O pins.
DIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input. After configuration is
complete, this pin becomes a user-programmed I/O pin.
DOUT
During configuration this pin is used to output serial-
configuration data to the DIN pin of a daisy-chained slave.
After configuration is complete, this pin becomes a user-
programmed I/O pin.
TCLKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to
the global clock net, and the global clock net should be
used as the primary clock source, this pin is usually the
clock input to the chip.
Unrestricted User I/O Pins.
I/O
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted I/
O pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 50 k
to 100 k
that
becomes active as soon as the device powers up, and
stays active until the end of configuration.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with
a 50 k
to 100 k
pull-up resistor.
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