參數(shù)資料
型號(hào)： XC3042A-6TQ144C
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 135 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 32/50頁(yè)
文件大?。?/td> 474K
代理商： XC3042A-6TQ144C
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-134
Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
Power
Power Distribution
Power for the LCA device is distributed through a grid to
achieve high noise immunity and isolation between logic
and I/O. Inside the LCA device, a dedicated V
CC
and
ground ring surrounding the logic array provides power to
the I/O drivers. An independent matrix of V
CC
and
groundlines supplies the interior logic of the device. This
power distribution grid provides a stable supply and ground
for all internal logic, providing the external package power
pins are all connected and appropriately decoupled. Typi-
cally a 0.1-
μ
F capacitor connected near the V
CC
and
ground pins will provide adequate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of
driving as much as 25 to 30 times that current in a best
case. Noise can be reduced by minimizing external load
capacitance and reducing simultaneous output transitions
in the same direction. It may also be beneficial to locate
heavily loaded output buffers near the ground pads. The
I/O Block output buffers have a slew-limited mode which
should be used where output rise and fall times are not
speed critical. Slew-limited outputs maintain their dc drive
capability, but generate less external reflections and inter-
nal noise.
S250
200
150
100
50
3 CLBs
(3-12)
4 CLBs
(4-16)
2 CLBs
(2-8)
1 CLB
(1-4)
XC3100-3
XC3000-125
CLB Levels:
Gate Levels:
300
Toggle
Rate
0
X3250
Figure 27. Clock Rate as a Function of Logic Complexity
(Number of Combinational Levels between
Flip-Flops)
1.00
0.80
0.60
0.40
0.20
SPECIFIED WORST-CASE VALUES
MAX COMMERCIAL (4.75 V)
MAX MILITARY (4.5 V)
– 55
MIN MILITARY (5.5 V)
MIN COMMERCIAL (4.75 V)
MIN COMMERCIAL (5.25 V)
TYPICAL COMMERCIAL
(+ 5.0 V, 25
°
C)
TYPICAL MILITARY
TEMPERATURE (
°
C)
– 40
– 20
0
25
40
70
80
100
125
N
X6094
MIN MILITARY (4.5 V)
相關(guān)PDF資料
PDF描述
XC3042A-7PC84I ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles
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XC3042A-7TQ144C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3042A-7TQ144I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3042A-6VQ100C 制造商:Xilinx 功能描述:
XC3042A7PC84C 制造商:XILINX 功能描述:New
XC3042A-7PC84C 功能描述:IC LOGIC CL ARRAY 4200GAT 84PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3042A-7PC84C0090 制造商:Xilinx 功能描述:
XC3042A-7PC84C0100 制造商:Xilinx 功能描述:
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