參數(shù)資料
型號(hào)： XC3042A-6TQ144C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 135 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 18/50頁(yè)
文件大小： 474K
代理商： XC3042A-6TQ144C
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-120
XC3020
XC3020A
XC3020L
XC3120
XC3120A
XC3030
XC3030A
XC3030L
XC3130
XC3130A
XC3042
XC3042A
XC3042L
XC3142
XC3142A
XC3064
XC3064A
XC3064L
XC3164
XC3164A
XC3090
XC3090A
XC3090L
XC3190
XC3190A
XC3195
XC3195A
Device
Gates
1,000 to
1,500
64
(8 x 8)
64
1,500 to
2,000
100
(10 x 10)
80
2,000 to
3,000
144
(12 x 12)
96
3,500 to
4,500
224
(16 x 14)
120
5,000 to
6,000
320
(20 x 16)
144
6,500 to
7,500
484
(22 x 22)
176
CLBs
Row x Col
IOBs
Flip-flops
Horizontal Longlines
TBUFs/Horizontal LL 9
Bits per Frame
(including1 start and 3 stop bits)
Frames
Program Data =
Bits x Frames + 4 bits
(excludes header)
PROM size (bits) =
Program Data
+ 40-bit Header
256
16
360
20
11
92
480
24
13
108
688
32
15
140
928
40
17
172
1,320
44
23
188
75
197
14,779
241
22,176
285
30,784
329
46,064
373
64,160
505
94,944
14,819
22,216
30,824
46,104
64,200
94,984
Clear or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as RESET,
bus enable or PROM enable during configuration. For
parallel Master configuration modes, these signals pro-
vide PROM enable control and allow the data pins to be
shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs
have TTL thresholds and can change to CMOS thresholds
at the completion of configuration if the user has selected
CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
Configuration Data
Configuration data to define the function and interconnec-
tion within a Logic Cell Array is loaded from an external
11111111
0010
< 24-Bit Length Count >
1111
0 <Data Frame # 001 > 111
0 <Data Frame # 002 > 111
0 <Data Frame # 003 > 111
. . .
. . .
. . .
. . .
0 <Data Frame # 196 > 111
0 <Data Frame # 197 > 111
1111
—Dummy Bits*
—Preamble Code
—Configuration Program Length
—Dummy Bits (4 Bits Minimum)
For XC3120
197 Configuration Data Frames
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
Postamble Code (4 Bits Minimum)
Header
Program Data
Repeated for Each Logic
Cell Array in a Daisy Chain
*The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits
X5300
Figure 19.
Internal Configuration Data Structure for an LCA Device.
This shows the preamble, length count and data frames
generated by the XACT Development System.
The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8] – (2
≤
K
≤
4) where K is a function of DONE and RESET timing selected. An additional 8 is added
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
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