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參數資料
| 型號： | XC3042A-6PQ100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 135 MHz, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 26/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3042A-6PQ100C |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-128
Peripheral Mode
X3031
ADDRESS
BUS
DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC
CS0
.
RDY/BUSY
WS
RESET
.
OTHER
I/O PINS
D0–7
CCLK
DOUT
M2
HDC
LDC
LCA
GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0
M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 k‰
*
IF READBACK IS
ACTIVATED, A
5-k‰ RESISTOR IS
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 23.
Peripheral Mode.
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead LCA
device, this data is loaded into a double-buffered UART-
like parallel-to-serial converter and is serially shifted into
the internal logic. The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the DOUT pin.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. RDY/BUSY
goes Low when a byte has been received, and goes High
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. If the shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
相關PDF資料 |
PDF描述 |
|---|---|
| XC3120A-09PC68C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-09PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-09PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-09PQ100C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-09PQ100C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC3042A-6TQ144C | 制造商:Xilinx 功能描述: |
| XC3042A-6VQ100C | 制造商:Xilinx 功能描述: |
| XC3042A7PC84C | 制造商:XILINX 功能描述:New |
| XC3042A-7PC84C | 功能描述:IC LOGIC CL ARRAY 4200GAT 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數:100 邏輯元件/單元數:238 RAM 位總計:3200 輸入/輸出數:80 門數:3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC3042A-7PC84C0090 | 制造商:Xilinx 功能描述: |
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