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Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.0) August 1, 2003
Product Specification
1-800-255-7778Module 3 of 4
4
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx
Application Note 623
for detailed information
on power distribution system design.
V
CCAUX
powers critical resources in the FPGA. Thus,
V
CCAUX
is especially susceptible to power supply noise.
Changes in V
CCAUX
voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756, available
at
www.support.xilinx.com
.
V
CCAUX
can share a power plane with 3.3V V
CCO
, but only if
V
CCO
does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. (More information on
SSO is available in Xilinx Answer Record 11713.)
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed over the recom-
mended operating conditions at the V
OL
and V
OH
test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V
CCO
with
the respective V
OL
and V
OH
voltage levels shown. Other
standards are sample tested.
Table 5:
Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
I
CCINTMIN
200
250
350
400
500
650
800
1100
I
CCAUXMIN
100
100
100
100
100
100
100
100
I
CCOMIN
50
50
100
100
100
100
100
100
Notes:
1.
Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
I
CCOMIN
values listed here apply to the entire device (all banks).
2.
Table 6:
DC Input and Output Levels
Input/Output
Standard
V
IL
V
IH
V
OL
V, Max
V
OH
V, Min
I
OL
mA
I
OH
mA
V, Min
V, Max
V, Min
V, Max
LVTTL
(1)
– 0.5
0.8
2.0
3.6
0.4
2.4
24
– 24
LVCMOS33
– 0.5
0.8
2.0
3.6
0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
90% V
CCO
90% V
CCO
Note 2
24
– 24
LVCMOS25
– 0.5
0.7
1.7
2.7
0.4
24
– 24
LVCMOS18
– 0.5
35% V
CCO
35% V
CCO
30% V
CCO
30% V
CCO
Note 2
65% V
CCO
65% V
CCO
50% V
CCO
50% V
CCO
Note 2
1.95
0.4
16
– 16
LVCMOS15
– 0.5
1.7
0.4
16
– 16
PCI33_3
– 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
Note 2
10% V
CCO
10% V
CCO
Note 2
Note 2
Note 2
PCI66_3
– 0.5
Note 2
Note 2
PCI–X
– 0.5
Note 2
Note 2
GTLP
– 0.5
V
REF
– 0.1
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.2
V
REF
+ 0.1
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
0.6
n/a
36
n/a
GTL
– 0.5
0.4
n/a
40
n/a
HSTL I
– 0.5
0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
REF
+ 0.6
8
– 8
HSTL II
– 0.5
0.4
16
– 16
HSTL III
– 0.5
0.4
24
– 8
HSTL IV
– 0.5
0.4
48
– 8
SSTL3 I
– 0.5
V
REF
– 0.6
8
– 8