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參數(shù)資料
| 型號(hào)： | XC2V500-6FG456C |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Virtex-II 1.5V Field-Programmable Gate Arrays |
| 中文描述： | FPGA, 768 CLBS, 500000 GATES, 820 MHz, PBGA456 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, MO-034AAJ-1, FBGA-456 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | XC2V500-6FG456C |
Virtex-II 1.5V Field-Programmable Gate Arrays
R
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
1-800-255-7778Module 1 of 4
3
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic designs. As shown in
Figure 1
, the programmable device is
comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
The internal configurable logic includes four major elements
organized in a regular array.
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Block SelectRAM memory modules provide large
18-Kbit storage elements of True Dual-Port RAM.
Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse and fine-grained clock phase
shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
programmable
elements,
including
the
routing
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
Input block with an optional single-data-rate or
double-data-rate (DDR) register
Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
Bi-directional block (any combination of input and
output configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V)
PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz)
GTL and GTLP
HSTL (Class I, II, III, and IV)
Figure 1:
Virtex-II
Architecture Overview
Global Clock Mux
DCM
DCM
IOB
CLB
Programmable I/Os
Block SelectRAM
Multiplier
Configurable Logic
DS031_28_100900
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PDF描述 |
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| XC2V500-6FG456I | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V3000 | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40 | Field-Programmable Gate Arrays |
| XC2V4000 | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V500 | Virtex-II 1.5V Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2V500-6FG456I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
| XC2V500-6FGG256C | 功能描述:IC FPGA VIRTEX-II 500K 256-FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-II 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2V500-6FGG456C | 功能描述:IC FPGA VIRTEX-II 500K 456-FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-II 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2V6000 | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
| XC2V6000-4BF957C | 功能描述:IC FPGA VIRTEX II 3M 957-FCBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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