Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Summary of Virtex
-II Features
Industry First Platform FPGA Solution
IP-Immersion Architecture
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Densities from 40K to 8M system gates
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420 MHz internal clock speed (Advance Data)
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840+ Mb/s I/O (Advance Data)
SelectRAM Memory Hierarchy
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3 Mb of True Dual-Port RAM in 18-Kbit block
SelectRAM resources
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Up to 1.5 Mb of distributed SelectRAM
resources
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High-performance interfaces to external memory
·
DDR-SDRAM interface
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FCRAM interface
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QDR
-SRAM interface
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Sigma RAM interface
Arithmetic Functions
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Dedicated 18-bit x 18-bit multiplier blocks
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Fast look-ahead carry logic chains
Flexible Logic Resources
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Up to 93,184 internal registers / latches with Clock
Enable
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Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
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Wide multiplexers and wide-input function support
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Horizontal cascade chain and Sum-of-Products
support
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Internal 3-state bussing
High-Performance Clock Management Circuitry
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Up to 12 DCM (Digital Clock Manager) modules
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Precise clock de-skew
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Flexible frequency synthesis
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High-resolution phase shifting
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16 global clock multiplexer buffers
Active Interconnect
Technology
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Fourth generation segmented routing structure
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Predictable, fast routing delay, independent of
fanout
SelectI/O-Ultra
Technology
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Up to 1,108 user I/Os
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19 single-ended standards and six differential
standards
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Programmable sink current (2 mA to 24 mA) per I/O
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Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
Differential Signaling
·
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
·
Bus LVDS I/O
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Lightning Data Transport (LDT) I/O with current
driver buffers
·
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
·
Built-in DDR Input and Output registers
Proprietary high-performance SelectLink
Technology
·
High-bandwidth data path
·
Double Data Rate (DDR) link
·
Web-based HDL generation methodology
Supported by Xilinx Foundation
and Alliance
Series Development Systems
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Integrated VHDL and Verilog design flows
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Compilation of 10M system gates designs
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Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
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Fast SelectMAP
configuration
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Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
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IEEE1532 support
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Partial reconfiguration
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Unlimited re-programmability
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Readback capability
0.15 μm 8-Layer Metal process with 0.12 μm
high-speed transistors
1.5 V (V
CCINT
) core power supply, dedicated 3.3 V
CCAUX
auxiliary and V
CCO
I/O power supplies
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
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Virtex-II 1.5V
Field-Programmable Gate Arrays
DS031-1 (v1.7) October 2, 2001
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Advance Product Specification
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