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參數(shù)資料
| 型號： | XC17256E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Configuration PROMs(配置PROM) |
| 中文描述： | 配置PROM的（配置可編程） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 124K |
| 代理商： | XC17256E |
DS027 (v3.1) July 5, 2000
Product Specification
1-800-255-77781
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
Low-power CMOS Floating Gate process
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Guaranteed 20 year life data retention
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
0
XC1700E and XC1700L Series
Configuration PROMs
DS027 (v3.1) July 5, 2000
0
8
Product Specification
R
Figure 1:
Simplified Block Diagram (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC
VPP
GND
DS027_01_021500
TC
OE
or
RESET/
OE/
RESET
CEO
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| XC17256ELPD8I | 功能描述:IC PROM SER I-TEMP 256K 8-DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| XC17256ELVO8C | 功能描述:IC 3V SER CFG PROM 256K 8-SOIC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
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