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參數(shù)資料
| 型號(hào)： | XC17256DDD8M |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | QPRO Family of XC1700D QML Configuration PROMs |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | XC17256DDD8M |
QPRO Family of XC1700D QML Configuration PROMs
DS070 (v2.1) June 1, 2000
Product Specification
1-800-255-7778AC Characteristics Over Operating Condition
(1,2)
Symbol
Description
XC1736D
XC1765D
XC17128D
XC17256D
Units
Min
Max
Min
Max
T
OE
OE to data delay
-
45
-
25
ns
T
CE
CE to data delay
-
60
-
45
ns
T
CAC
CLK to data delay
-
150
-
50
ns
T
OH
Data hold from CE, OE, or CLK
(3)
0
-
0
-
ns
T
DF
CE or OE to data float delay
(3,4)
-
50
-
50
ns
T
CYC
Clock periods
200
-
80
-
ns
T
LC
CLK Low time
(3)
100
-
20
-
ns
T
HC
CLK High time
(3)
100
-
20
-
ns
T
SCE
CE setup time to CLK (to guarantee proper counting)
25
-
20
-
ns
T
HCE
CE hold time to CLK (to guarantee proper counting)
0
-
0
-
ns
T
HOE
OE hold time (guarantees counters are reset)
100
-
20
-
ns
Notes:
1.
2.
3.
4.
AC test load = 50 pF
All AC parameters are measured with V
IL
= 0.0V and V
IH
= 3.0V.
Guaranteed by design, not tested.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200mV from steady state active levels.
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE
TSCE
THCE
THOE
TCAC
TOH
TDF
TOH
THC
DS027_03_021500
TCYC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC1736DDD8M | QPRO Family of XC1700D QML Configuration PROMs |
| XC1765DDD8M | QPRO Family of XC1700D QML Configuration PROMs |
| XC1700E | Configuration PROMs |
| XC1701LPC20C | Configuration PROMs |
| XC1701LPC20I | Configuration PROMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC17256DJI | 制造商:XIL 功能描述:XILINXNEW STOCK TUBES |
| XC17256D-PC20C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XC17256D-PC20I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XC17256D-PD8C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XC17256D-PD8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
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